1. Field of the Invention
The present invention relates to a semiconductor device a the production method therefor, and, particularly to a semiconductor device of a type called a system-in-package (SiP), which is packaged at a wafer level, and a production method therefor.
2. Description of the Related Art
Demands for more compact, thinner and lighter portable electronic devices, such as digital video cameras, digital cellular phones, and notebook computers, only get stronger. To respond thereto, seven tenths of a reduction has been realized in three years in a recent VLSI and other semiconductor devices, while studies and developments have been made on the significant issue of how to improve packaging density of components on a mounting board (printed wiring board) in an electronic circuit device wherein such a semiconductor device is mounted on a printed wiring board.
For example, the package type of a semiconductor device has shifted from the lead-inserted type, such as a dual inline package (DIP), to the surface-mounted type. Furthermore, a flip-chip mounting method for providing a bump (protruding electrode) made of solder or gold on a pad electrode of a semiconductor chip and connecting to the wiring board via the bump with the surface facing downward has been developed.
In the above semiconductor device, when forming multilayer wiring, also called rewiring layers, on the semiconductor substrate (chip), for example, an insulating layer is formed to be a film thickness of 1 μm or less on a surface of a semiconductor wafer formed with a transistor and other semiconductor elements by the chemical vapor deposition (CVD) method, the sputtering method, the thermal oxidization method or the spin coating method, etc., and dicing processing is performed to obtain a small piece of semiconductor device.
In the above production method, even when a step is generated on the insulating layer and warps arise on the wafer, it is sufficient to pay attention only to the blade and chipping at the dicing stage and it is unnecessary to pay attention to the step disconnection of a resist and warps of the wafer.
Furthermore, development has been advanced to a complicated type of package called a system-in-package (SiP) wherein a passive element, such as a coil, and other semiconductor chips are buried in an interlayer of an insulating layer for insulating rewiring layers formed on a semiconductor substrate (chip) and packaged at a wafer level.
As a production method of the SiP, for example, a method of forming as the insulating layer of the rewiring layers an insulating layer made of a polyimide resin and an epoxy resin, etc., to be a film thickness of 10 μm or less by the spin coating method on the surface of the semiconductor wafer formed with a transistor and other semiconductor element and performing dicing processing to obtain a small piece has been widely used.
Here, in the case where property values of the insulating layer are different in an elastic modulus and a thermal expansion coefficient from those in the semiconductor made by silicon, etc., a method of removing a resin on a scribe line in advance and cutting on the exposed scribe line to obtain a small piece is used.
In the production method of the SiP as above, in the case where the insulating layer of the rewiring layers is made to be a multilayer of, for example, three layers or more, when assuming that a film thickness of one layer is 10 μm at minimum, the thickness becomes 30 μm by putting the three layers together, so that it becomes relatively impossible to ignore the film thickness of the insulating layer of the rewiring layer in the case where, for example, a silicon substrate is made to be as thin as 50 μm or less.
Furthermore, in the case of forming a coil and other passive elements in an interlayer of the insulation layer of the rewiring layers in the SiP structure and in the case of burying a semiconductor chip, the film thickness of the whole insulating layer of the rewiring layers has to be 50 μm or more, and an effect given to warps of the semiconductor wafer becomes large.
When warps arise on the semiconductor wafer, an adsorbent error and a conveyance error may be caused in a production facility and breakage and a decline of the yield may also be brought. Furthermore, a disadvantage of a decline of secondary connection reliability is unfavorably caused due to residual stress.